Manatee
Start date:? 29.09.2020
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Funded by: 新万博体育下载_万博体育app【投注官网】 of Augsburg, CERCIRAS COST Action no. CA19135
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Local head of project: Prof. Dr. Sebastian Altmeyer
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Local scientists:? Dr. Florian Haas, Axel Wiedemann
Abstract
Research on memory hierarchies regarding the non-functional requirements in embedded multicore systems demands for a framework to support the prototyping and evaluation of new methods. In current multicore processors, accesses on shared resources by arbitrary tasks lead to interferences, which can result in timing violations of high-priority tasks. However, incorporating all potential interferences in the schedulability analysis leads to an enormous overestimation of the task execution times, and requires a full analysis of all tasks running on the system. Enhancements in the memory hierarchy can provide isolation to restrict potential interferences, thus improving the worst-case performance. To research on modifications in the memory hierarchy of a multicore processor, a prototyping and evaluation framework is required. With Manatee we are able to offer this framework.
Description
Manatee (Multicore interference ANAlysis Tool for Embedded soc Evaluation) offers support for embedded multicore SoC design when WCET does matter.
Our tool is able to provide the developer with a steady awareness of shared resource conflicts even during early prototyping.
On multicore architectures these conflicts occur frequently and often increase execution times.
Manatee integrates an automated development workflow leveraging Chipyards hardware design capabilities and continuously measures and visualises these conflicts.
Links
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Manatee - visualiser?(currently takes about 2 minutes to load) - Shows example measurements with Manatee's own integrated visualisation tool
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